1. Field of the Invention
The present invention pertains to a novel method for manufacturing a semiconductor device, and in particular a metal oxide semiconductor (MOS) device having source and drain of a lightly-doped drain (LDD) structure. The invention also relates to a semiconductor device per se fabricated by such a method.
2. Description of the Related Art
Due to an increased requirement towards larger integration of MOS memories in recent years, it has been desired to shorten a gate length or channel length in MOSFET. However, when a channel length is shortened, the intensity of electric field in the channel region increases to generate hot electrons in the vicinity of the drain, which may be entrapped into the gate oxide to cause deterioration of performance, such as variation in threshold voltage. Furthermore, due to the shortening of the channel length, depletion layers extending from the drain and source may reach the place immediately underneath the gate to lower the potential barrier in the channel region. As a result, the threshold voltage may decrease to deteriorate the drain-source pressure resistance. In order to avoid these various undesirable effects, including problems of hot electrons, accompanied with the shortening of channel lengths (hereinafter referred to as "short channel effects" in general), there has been proposed MOSFET of LLD structure which are manufactured by means of a self-aligned pocket implantation technique. This technique involves effecting a selective ion implantation into the regions in the vicinity of the gate which contact the source and drain regions and are constituted by a region of impurity with low concentration and a region of impurity with high concentration adjacent thereto, to thereby form impurity regions (pocket regions) of p-type (or n-type), in order to reduce the intensity of electric field at the source and drain-channel interface and to increase the pressure resistance.
For example, in the case where an n-channel MOSFET is manufactured, a gate oxide 102 is first deposited on a p-type semiconductor substrate 101, and a gate electrode 103 of a polysilicon having a patterning thereon is formed thereon, as schematically shown in FIG. 1(a). Thereafter, while permitting the gate electrode 103 to function as a mask, n-type impurity ions are implanted into the semiconductor substrate 101 to define n- regions 104 at areas adjacent to the surface of the semiconductor substrate 101, and p-type impurity ions are implanted into the semiconductor substrate 101 to define p.sup.+ regions 105 underneath the n- regions 104.
Subsequently, as depicted in FIG. 1(b), a silicon oxide is deposited by means of chemical vapor deposition (CVD) process on the gate electrode 103 and the gate oxide 102 exposed, and then an anisotropic etching is effected by means of a dry etching process to form spacers 106 at the opposite side walls of the gate electrode 103. Thereafter, by implanting n-type impurities while permitting these spacers 106 and the gate electrode 103 to serve as masks, n+ regions 107 and n regions 108 are formed at areas adjacent to the surface of the semiconductor substrate 101. Thus, that portion of each p+ region 105 which is located underneath a respective n- region 104 prevents the depletion layer of the drain and source region from extending to thereby inhibit a drop in threshold voltages.
In the aforementioned process, however, the n- regions 104 are formed by the implantation of n-type impurities and p-type impurities employing the same mask. Consequently, it is difficult to optimally control the impurity concentration in the n- regions 104 underneath the spacers 106, and its stability is poor. Furthermore, in the vicinity of each p+ region 105 underneath a respective n-region 108, there is a significant difference between the n-type impurity concentration and p-type impurity concentration, resulting in deterioration of the pressure resistance and leakage performance thereat.
In order to solve these problems, Japanese Laid-Open Patent Application No. Hei6-326123, has proposed an improvement in the conventional semiconductor-manufacturing method.
In the manufacturing technique disclosed therein, as shown in FIG. 2(a), a gate oxide 202 is deposited on a semiconductor substrate 201, and a patterned gate electrode 203 including a polysilicon film 203a and a silicon oxide film 203b is formed thereon. Subsequently, while permitting the gate electrode 203 to serve as a mask, n-type impurity ions are implanted into the semiconductor substrate 201 to define n- reduced concentration impurity regions 204 at areas adjacent to the surface of the semiconductor substrate 201. During the implantation, a large angle tilt implantation (LATI) technique is utilized to overlap the n- reduced concentration impurity regions 204 with the gate electrode 203.
Thereafter, as depicted in FIG. 2(b), a silicon oxide is deposited by means of CVD process on the gate electrode 203 and the gate oxide 202 exposed, and then an anisotropic etching is effected by means of a dry etching process to provide spacers 205 at the opposite side walls of the gate electrode 203. Thereafter, by an ion-implantation method which permits these spacers 205 and the gate electrode 203 to serve as masks, n+ high concentration impurity regions 206 are formed at areas adjacent to the surface of the semiconductor substrate 201. Further, as depicted in FIG. 2(c), after a polysilicon is deposited by means of CVD process, an etching is effected by means of a dry etching method to define a polysilicon film 207 so as to remain only on the areas where the source and drain regions are formed. Then, as shown in FIG. 2(d), the spacers 205 are selectively removed, and p-type impurity ions are implanted into the semiconductor substrate 201 to define p+ pocket regions 208 in the regions immediately underneath the spacer-removed regions.
A MOSFET of a LDD structure having the p+ pocket regions 208 only at the desired portions can thus be obtained. In the foregoing, the impurity concentration for the n- reduced concentration impurity regions 204 immediately above the p+ pocket regions 208 can be easily set by the difference between the impurity concentration of the n-type impurity ions to be first implanted and the impurity concentration of p-type impurity ions to be implanted at the formation of the p+ pocket regions 208. Furthermore, the pressure resistance and leakage performance for the regions situated at the bottom of the n+ high concentration impurity regions 206 will not be deteriorated by the provision of the p+ pocket regions 208.
In the aforesaid manufacturing method of MOS devices, however, the gate electrode 203 is of a multi-layered structure which requires a considerable height. Accordingly, its patterning is difficult. In addition, it is difficult to control the formation and removal of the polysilicon film 207, and upon the selective removal of the spacers 205, the configuration of the gate electrode 203 or the like is influenced. Therefore, the manufacturing process becomes complicated, thereby increasing the cost, deteriorating the yield, and lowering the reliability.